EDN

Decreasing the Cost of Test with Automatic Test Pattern Generation

Success in the electronics business hinges on producing high-quality products and using the most cost-effective methods to do so. As the number of devices on integrated circuits continues to double ...
Semiconductor Engineering

Reducing Chip Test Costs With AI-Based Pattern Optimization

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
Hackaday

Pocket-sized Test Pattern Generator Helps Check Those CRTs

Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one ...
Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...