EDN

Reversing the SoC Design Process

It is obvious that IP-based system-on-chip (SoC) design or at least some form of “reuse methodology” is the way to address increasingly complex designs in shrinking time-to-market windows. But with ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...
Nasdaq

Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

Cadence 20.1 digital full flow tuned for Samsung Foundry advanced-process nodes, enabling optimal PPA and first-pass silicon success HPC reference flows based on iSpatial technology enable rapid ...
Forbes

Cadence Brings Big Data And AI Analytics To SoC Verification

Forbes contributors publish independent expert analyses and insights. I write about disruptive companies, technologies and usage models. Over the years, the cost of designing a system on chip (SoC) ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...
Semiconductor Engineering

Crossing The Chasm: Uniting SoC And Package Verification

Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, ...
Embedded

How virtual prototypes aid SoC hardware design

The world of the hardware design engineer has changed dramatically in recent years. Designers no longer sit and code RTL in isolation to meet a paper specification, and then wait for a hardware ...
Electronic Design

Interview: Harry Luan Addresses SoC Design Challenges

Harry Luan, Kilopass’ chief technology officer and vice president of R&D, is an expert in CMOS/non-volatile memory (NVM) device physics, modeling, optimization and characterization for technology ...
Design-Reuse

Do SoC Architects Have to Get Physical?

With the rapid adoption of the 16/14nm FinFET semiconductor manufacturing processes, the SoC architect’s job is becoming more difficult. Traditionally, architects were responsible for key decisions ...
Business Wire

Cadence Collaborates With Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence ® digital 20.1 full flow for Samsung Foundry’s advanced-process ...