EDN

Recycle RTL test benches to verify Transaction-Level IP Models

System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...
EDN

RTL test objects at ITC

Testability strategies able to handle 65-nm and denser processes highlighted EDA firms’ presentations at last week’s International Test Conference. In particular, power-aware and small-delay-defect ...
Design-Reuse

Moving DFT to RTL overcomes test vector issues

In the IC design flow, design-for-test is often an afterthought. First, the design is coded, then simulated, then synthesized, and only after all that - usually months into the design cycle - it's ...
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
New Electronics

Siemens streamlines design-for-test tasks with Tessent RTL Pro

Siemens Digital Industries Software has unveiled the Tessent RTL Pro, a software solution developed to help integrated circuit (IC) design teams streamline and accelerate a broad array of critical ...
Electronic Design

A flexible flow for inserting embedded compression logic in RTL

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...
Electronic Design

How to Become an RTL Simulation Expert vs. Hardware Emulation Expert

In Part 1, we reviewed the process of designing a modern hardware emulation platform. Here, we’ll look at the skills and training that are necessary to become a simulation expert and an emulation ...