As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...

If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...

System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges.

New design languages and new chips and systems mean a whole new set of design gotchas for today's developers. Once-simple tasks become difficult and, thankfully, once-difficult tasks become easy. This ...

Editor's note: Consultant and ASIC designer Tom Moxon has evaluated deep submicron IC design flows using open-source cores and new EDA tools. He will report his findings in a five-part article series ...

Historically, exploiting FPGA or ASIC implementation of DSP algorithms has been the domain of companies with highly-skilled designers and large budgets. Now, a new generation of tools is bringing ...