High-speed serial interfaces such as CEI, XFP/XFI, 10-Gbit/s Ethernet, and both 4-Gbit/s and 10-Gbit/s Fibre Channel are creating demands for test equipment that can give you detailed performance ...

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most ...

Right before the Christmas holidays a customer provided the headline for this blog post by making that exact statement. Now let’s look at what he was talking about. Every once in a while, I am ...

The potential causes of signal integrity problems in a device are wide ranging, including the physical layout of the design, underperforming components, and accumulative affects with multiple causes.

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...