PI Introduces Miniaturized Alignment Engine Platform for Scalable, Parallel E/O Wafer-Level Test

PI Introduces Miniaturized Alignment Engine Platform for Scalable, Parallel E/O Wafer-Level Test Parallel piezo aligners with fly height sensors enable faster PIC wafer testing.
Semiconductor Engineering

Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, ...
EDN

Using vision to align wafer stacks

When Ben Wells, president of Wells R&D (Lincoln, MA), a maker of custom testing solutions for the semiconductor and optical industries, was building a test instrument, he needed to way to stack and ...
Nasdaq

Teradyne Announces Production System for Double-Sided Wafer Probe Test for Silicon Photonics

NORTH READING, Mass.--(BUSINESS WIRE)-- Teradyne, a leading provider of automated test equipment, has partnered with ficonTEC, a global leader in production solutions for photonics assembly and test, ...
Semiconductor Engineering

Intra-Field Stress Impact on Global Wafer Deformation

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., ...