The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

This strategic move integrates ASTER’s advanced "shift-left" design for test (DFT) functionality directly into Siemens' ...

Memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to meet ...

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

Join us on Wednesday, December 15 at noon Pacific for the Design for Test Hack Chat with Duncan Lowder! If your project is at the breadboard phase, or even if you’ve moved to a PCB prototype, it’s ...

Huge transistor counts, rising on-chip clock rates, the relentlessly escalating levels of integration in systems-on-chip, and the new types of defects seen in deep-submicron and nanometer processes ...

Connected devices and systems have become an integral part of our everyday life and we take this for granted. Finding the fastest way to our destination with a smartphone, reading the news on a tablet ...