EDN

Calibrate scope jitter using a transmission-line loop

Digital-clock-period jitter is the variation in the period of a clock cycle compared with a nominal (average of many cycles) clock period. To accurately measure period jitter using an oscilloscope, ...
Embedded

Dealing with PLL clock jitter in advanced processor designs: Part 3

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be ...
EDN

Clock jitter and the crystal oscillator

http://www.cardinalxtal.comThe term “frequency jitter” has become popular in the last few years to define the short-term stability of a frequency source. A ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal ...
Business Wire

PCI Express Clock Jitter Measurement Tool from Silicon Labs Simplifies Timing Design

AUSTIN, Texas--(BUSINESS WIRE)--Silicon Labs (NASDAQ: SLAB) has introduced a free software tool that enables engineers to quickly and easily measure PCI Express® (PCIe®) clock jitter from an ...
Electronic Design

Communications Timing: Pruning clock-tree problems

The interpretation of signals within a synchronous digital communications system relies upon timing. Whether a 1 or a 0 is read by a receiver depends entirely on when the signal is sampled, and sample ...
Electronic Design

Simplify System Clocking with Programmable Multi-Output Clock Generators

Today’s complex system boards often contain application-specific processors, high-speed general-purpose processors, and multiple system-on-a-chip designs. Each of these high-performance circuits may ...
Design And Reuse

Creating a Frequency Plan for a System using a PLL

Perceptia Devices is an IP and design services provider, based in Sydney, Australia and Silicon Valley. It is focused on PLLs for RF systems and demanding clocking applications. Perceptia offers a ...
Seeking Alpha

Skyworks Sets New Benchmark in Ultra-Low Jitter Clock Buffers for High-Speed Connectivity

New SKY53510/80/40 Family of Clock Fanout Buffers are Purpose-Built for Data Centers, Wireless Networks, and PCIe Gen 7 Applications IRVINE, Calif.--(BUSINESS WIRE)-- Skyworks Solutions, Inc. (SWKS), ...