EDN

Binary Clock Design

The Basic Stamp Homework Board (BSHWB) microcontroller, the PIC16C57, is a surprisingly useful and somewhat powerful microcontroller which I decided to choose for designing a binary clock, along with ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Hackaday

Simple NTP Clock Uses Custom RGB 7-Segment Displays

A great majority of hackers build a clock at some point. It’s a great way to get familiar with electronics and (often) microcontrollers, and you get to express some creativity along the way. Plus, you ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
Semiconductor Engineering

Can RTL Clock Power Be Accurate Enough For Sub-20nm Multi-GHz Designs?

Can RTL power adequately model the key physical aspects of clocks in order to make reliable power-related decisions? What about further complexities that sub-20nm high-performance designs pose? The ...